Regviz

Silicon Labs /BGM240PB32VNN /MODEM_S /ADPC9

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ADPC9

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Silicon Labs/EFR32MG24A010F1536GM40/MODEM_S/ADPC9#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ADBBSSAMPAVGLIM0ADBBSSAMPTHR0 (DISABLE)ADBBSSSYNCEN 0ADBBSSUPTHR 0ADBBSSDNTHR

ADBBSSSYNCEN=DISABLE

Description

No Description

Fields

ADBBSSAMPAVGLIM

ADBBSSAMPAVGLIM
ADBBSSAMPTHR

ADBBSSAMPTHR
ADBBSSSYNCEN

Enable sync of BBSS

0 (DISABLE): Do not synchronize BBSS to antenna switching

1 (ENABLE): Synchronize BBSS to anetnna switching
ADBBSSUPTHR

BBSS increase threshold
ADBBSSDNTHR

BBSS decrease threshold

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data